The output of flip-flops and other types of docked synchronous components change state responsive to the active edge of a clock. Compliance of setup and hold times relative to the dock edges permits the flip-flops' output to correctly change state. The setup time is the amount of time that the input data signal must be at its correct logic level before the active edge of the clock. The hold time is the amount of time that the input data must remain at its correct logic level after the active edge of the dock,
Within a given clock signal cycle, the input data must remain stable during both the setup and hold times and thus the input data can only change state during that portion of the clock signal that is outside the setup and hold time periods. As clock frequencies increase and thus the period of each clock signal decreases, the setup and hold times represent a larger portion of the clock cycle which means that less time is available in each clock cycle during which the input data is permitted to change state without violating the setup and hold timing requirements.